Gourt > Computers > Hardware > Programmable Logic > CPLD
CPLD stands for Complex Programmable Logic Device. It is a programmable logic device with complexity between that of FPGAs and PALs, and architectural features from both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.
Features in common with PALs:
- Non-volatile configuration memory. Unlike an FPGA, an external configuration PROM isn't required, and the CPLD can function immediately on system start-up.
- For all but the largest devices, routing constrains most logic blocks to have input and output signals connected to external pins (little opportunity for internal state storage or deeply layered logic).
Features in common with FPGAs:
- Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
- Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions (such as integer arithmetic).
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| - 4 digit counter implemented on two Xilinx CPLDs. All CPLD code has been autogenerated by our B Squared Logic to ABEL ... | |
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