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Very Long Instruction Word or VLIW refers to a CPU architectural approach to instruction level parallelism. Scalar architectures execute one instruction at a time, usually in the exact same order in which they appear in the original program. Superscalar architectures attempt to speed up programs by reordering and/or executing instructions in parallel, using specialized and often complex hardware to discover these opportunities while the code executes.
In contrast, VLIW architectures execute instructions in parallel based on a fixed schedule determined when the code is compiled. They do not contain the specialized hardware associated with superscalar CPUs. Rather, they rely on compilers to analyze and schedule instructions in parallel. As a result, VLIW CPUs offer significant computational power with less hardware complexity (but greater compiler complexity) than is associated with most superscalar CPUs.
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Meta Description: [ Transmeta's not the only chip maker with code-morphing software. IBM Research is developing its own way to ensure VLIW chip compatability. ]
Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools - By Joseph A. Fisher, Paolo Faraboschi, Cliff Young; Morgan Kaufmann, 2004, ISBN 1558607668. Technology is removing the gap between embedded and VLIW computing: high-performance methods that seemed too costly for embedded use have become feasible and popular. Book description, reviews, biographies.
Very Long Instruction Word - Growing entry, with links to many related topics. [Wikipedia]
VLIW at IBM Research - Very-Long Instruction Word architectures: an alternative way to organize processors. Instead of the trend toward hardware making complex decisions for scheduling machine-level instructions in programs, VLIW systems do scheduling at compile time.
Meta Description: [ VLIW at IBM Research ]
VLIW Processors and Trace Scheduling - Descriptions, history, examples, references; in HTML, PDF, and in: The Computer Engineering Handbook, by Vojin Oklobdzija, CRC Press, 2001, ISBN 0849308852.
Meta Description: [ Very Large Instruction Word Architectures (VLIW Processors and Trace Scheduling) ]
