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This article is about computer architecture; for use of the acronym RISC in biology, see RNA-induced silencing complex.

The reduced instruction set computer, or RISC, is a microprocessor CPU design philosophy that favors a simpler set of instructions that all take about the same amount of time to execute. The most common RISC microprocessors are AVR, PIC, ARM, DEC Alpha, PA-RISC, SPARC, MIPS, and IBM's PowerPC. The idea was inspired by the discovery that many of the features that were included in traditional CPU designs to facilitate coding were being ignored by the programs that were running on them. Also these more complex features took several processor cycles to be performed. Additionally, the performance gap between the processor and main memory was increasing. This led to a number of techniques to streamline processing within the CPU, while at the same time attempting to reduce the total number of memory accesses.

Pre-RISC design philosophy


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Beyond RISC: The Post-RISC Architecture - Today's RISC processors are so far from RISC roots that they are no longer truly RISC. [Michigan State University, Department of Computer Science]

404 ColdFire Development Resources - Source code for a GCC variant, with optimizations, bug fixes for Freescale Semiconductor (Motorola) variable length RISC 68K series processors; information on how to use GNU C, RTEMS, and other free tools for embedded development.

Hyperstone Electronics GmbH - RISC/DSP processors, flash memory controllers and cards (and compact cards), ASIC design, IP hardware, biometric devices, digital still cameras.
Meta Description: [ Hyperstone: RISC/DSP microcontroller, microprocessor for Industrial Automation, Security and Surveillance Systems, Multi-Media and Flash Memory Applications ]

Reduced Instruction Set Computer - Growing entry, with links to many related topics. [Wikipedia]

Reduced Instruction Set Computer - Brief, very clear definition, with links to related issues and processors. [FOLDOC]

RISC Architecture - Sophomore college project. Basic clear explanations of: What is RISC, MIPS processors, Pipelining, RISC vs. CISC, some recent developments, readings.

RISC vs. CISC - Document based on John Mashey (SGI) compilation of comp.arch debates, in one HTML document for easier reading, more so tables; original text and formats preserved where possible.

RISC vs. CISC: The Post-RISC Era - Detailed, balanced, historical analysis. [Ars Technica]
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